A Central Processing Unit (CPU), also known as a processor, microprocessor, controller, and the like, is a digital electronic circuit operative to execute software in the form of a series of stored instructions. A CPU, usually integrated into one or more integrated circuits, or “chips,” is the “brain” of virtually all computers, as well as a vast array of electronic devices, such as cellphones, PDAs, e-readers, GPS receivers, ATMs, and the like. CPUs are integrated into vehicles and aircraft, appliances, vending machines, and industrial equipment. In short, CPUs are ubiquitous. CPUs vary in size (both physical and data word width), functionality, frequency of operation, and other parameters. CPUs deployed in portable, battery-powered devices are often designed with power-saving provisions, such as variable frequency and the ability to put one or more segments into dormant or “sleep” mode to conserve power. High performance may be achieved in some CPUs by designing two or more “cores,” or computational units, into the same CPU. This achieves the processing power of two CPUs, at a reduced cost compared to two separate CPUs, by high integration and sharing many peripheral resources. Many CPUs include memory circuits integrated on-chip with the core(s), and most CPUs additionally are tightly coupled to external memory for program and data storage.
To achieve maximum performance from a given CPU, it is necessary to provide a power supply with a voltage as stable as possible. For each operating frequency, there is a corresponding minimum voltage level required of the power supply to ensure correct operation. If there is noise on the power supply, then the nominal voltage of the power supply must be increased, to ensure that the supplied voltage does not dip below the minimum required voltage. However, the power supply voltage cannot simply be raised indefinitely to reach the requirement of a particular frequency. A higher supply voltage increases the power consumption, reducing battery life (when applicable) and increasing the heat generated. Additionally, reliability concerns enforce a maximum voltage for each integrated circuit manufacturing technology
Power supply noise, or high-frequency fluctuations in the ideally DC-level power supply voltage, arises from several sources. Current transients due to changes in activity on the CPU (for example when the CPU wakes up from a dormant mode due to an interrupt) can generate power supply noise. Noise may also arise from imperfections in the power supply itself, such as the ripple on a Switch Mode Power Supply (SMPS). Additionally, high-frequency current transients due to the switching of the logic inside the CPU will cause noise on the power supply voltage. In this case, the noise will have a large component with the same frequency as the CPU clock signal. However, as different instructions and data will cause slightly different patterns of logic switching, there are also lower-frequency components in the current transients generated from logic switching.
Several measures may be taken to mitigate the impact of noise on the CPU power supply. For example, the power supply network may be optimized to provide the lowest possible impedance. This may be done by optimizing the routing or power supply lines (to reduce resistance and inductance) and adding capacitive decoupling at all levels, e.g., on the PCB, on package substrate and on the silicon die. Capacitive decoupling provides a path to ground for the high-frequency noise component on the power supply lines, while isolating the DC level from ground. Transient currents may be reduced by increasing the frequency of the CPU in steps when the CPU is “awoken” from a dormant state. The CPU power supply voltage may also be monitored, and the CPU frequency reduced when the voltage falls below a predetermined threshold.
Another limitation on the CPU maximum frequency arises from On-Chip Variation (OCV). OCV refers to the variation in timing on signals—primarily digital clock signals—as they propagate across an integrated circuit. OCV limits the effective frequency by increasing defensive design parameters, such as set-up and hold times, necessary to account for uncertainty in arrival time of clock edges. OCV is particularly a problem when the source and destination flip-flops for a signal path are clocked by largely independent clock trees. The clock trees may be separate due to various reasons. High level clock gating (i.e., turning off clocks to different circuits, or to different parts of a CPU) enforces separate clock trees between regions with different clock gating conditions. Also, the level of separation of the clock tree between different flip-flops will always vary, and by necessity some paths will have largely independent clock paths.
Measures may be taken to mitigate the impact of OCV on the CPU operating frequency. One example is the use of a global clock mesh instead of a standard clock tree. However, a clock mesh dramatically increases power consumption over that of a clock tree, and is not compatible with high level clock gating or the use of separate power domains.
The Background section of this document is provided to place embodiments of the present invention in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section.